Complementary Energy Path Adiabatic Logic

ABSTRACT

A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a logic circuit, and particularly to acomplementary energy path adiabatic logic (CEPAL) capable of improvingthe reliability, energy efficiency, and increasing the throughputthereof.

2. Description of Related Art

The conventional reversible adiabatic logic has a control signalfeedback from the next stage thereof. Thus, design cost for largesystems using such logic is expensive. Although an irreversibleadiabatic logic has the advantage of no need of use of the next-stagecontrol signal in implementation, almost all such circuits have thecharacteristics of dynamic circuit and the problem of relatively higherswitch activities, which is related to a ratioed logic. In addition,most of the irreversible adiabatic logic circuit has the requirements ofmulti-phase and multi-clock, making itself not favorable to circuitdesigners in terms of design complexity and required area forrealization. In response to that, a QSERL circuit has been suggested toovercome the shortcomings [1]-[2] of the irreversible logic circuitabove mentioned. The conventional QSERL circuit mainly comprises anevaluation network and a power clock network. The power clock networkcomprises a diode-connected P-type metal-oxide-semiconductor (MOS)transistor, a diode-connected N-type MOS transistor and two power clocks(or two diodes and two power clocks). The evaluation network is a logiccircuit combined with P and N-type MOS transistors. In operation, theevaluation network follows the two inputted power clocks to performevaluation and operation jobs. As shown in FIG. 7, the power clocknetwork has MOS transistors QP1, QN1, QP2 and QN2 and four invertingcircuits work with it to jointly realize a QSERL inverter chain with theMOS transistors QP1, QN1, QP2 and QN2 commonly, wherein the inverterchain is formed by four cascaded stages of inverters. In the inverterchain, the first, second, third and four-stage inverters are composed ofMOS transistors MP5 and MN5, MP6 and MN6, MP7 and MN7, and MP8 and MN8,respectively. This QSERL has simple and static logic-likecharacteristics, lending itself to have considerably reduced designcomplexity and switch activity. The design with the complementary powerclocks leads itself to have higher energy efficiency as compared withthe prior arts of more clocking phases. However, such QSERL has toalternatively maintain a “hold” phase causing the output floated inoperation, and thus has the reliability issue regarding the operationalcorrectness to be considered. Although this problem can be overcome byintroducing an additional feedback keeper controlled by the additionalclocking signals into each of the QSERLs, the energy efficiency iscorrespondingly reduced. Furthermore, the required implementation areaand overhead for the additional keepers and the control signals mayconsiderably limit the QSERL's applications. As may be seen from above,the conventional adiabatic logic still has problems to be solved andthus has to be improved.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a complementaryenergy path adiabatic logic (CEPAL) not only having the advantages ofthe QSERL but also almost eliminating the need of maintaining a “hold”phase under the same operation conditions, thereby capable of improvingreliability and increasing throughput thereof. It is another object ofthe present invention to provide a complementary energy path adiabaticlogic avoiding both the ratioed logic and relatively higher switchactivities of the prior arts.

It is yet another object of the present invention to provide acomplementary energy path adiabatic logic capable of considerablyreducing complexity and required area in implementation and eliminatingthe reliability concern caused by the floated output.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an embodiment of the present invention.

FIG. 2 is a schematic diagram exemplifying the power clocks of the CEPALand QSERL circuits. The corresponding operational phases for the QSERLcircuit are marked.

FIG. 3 is a schematic diagram of a CEPAL-based multiple cascaded logiccircuits in which a common power clock is used, according to the presentinvention. FIG. 4 is a schematic diagram of a CEPAL-based four-stageinverter chain in which a common power clock is used, according to thepresent invention.

FIG. 5( a) and (b) are, respectively, a sketch and waveforms showing anoise tolerance analysis in the four-stage inverter chains of QSERL andCEPAL, according to the present invention.

FIG. 6 is a schematic diagram of suitable types of power clock andinverted power clock.

FIG. 7 is a schematic diagram of the four-stage inverter chain of QSERLwith a power clock network in common.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1 to FIG. 6, a novel complementary energy pathadiabatic logic (CEPAL) is described in the present invention. Thecomplementary energy path adiabatic logic comprises an evaluationnetwork and a power clock network. The power clock comprising a firstP-type MOS transistor 10 and a second P-type MOS transistor 40, as wellas a first N-type MOS transistor 20 and a second N-type MOS transistor30. The evaluation network is a logic circuit composed of P- and N-typeMOS transistors. The evaluation network, designed in accordance with theprinciple of static complement metal-oxide-semiconductor (CMOS) circuit,is used to perform evaluation based on the input signals and powerclocks. The following will be dedicated to particular features of thecomplementary energy path adiabatic logic in details.

Each of the transistors involved in the power clock network acts as anactive diode. The power clock input 50 has its phase opposite to that ofthe complementary power clock input 60. These MOS transistors 10, 30 and20, 40 receive a power clock and an inverted complementary power clock,respectively. The complementary energy path adiabatic logic can achievethe evaluation purpose in accordance with the power clock, thecomplementary power clock, and the inputs of the evaluation network. Incomparison with the QSERL counterpart, presented in this invention canlead to a relatively lower energy dissipation.

The evaluation network of the complementary energy path adiabatic logicmay be any of the logic circuits performing predefined functions.

In an embodiment, the logic circuit may be an inverter logic circuit.

In an embodiment, the logic circuit may be a four-stage inverter logiccircuit.

In an embodiment, the logic circuit may be an NOR logic circuit.

In an embodiment, the logic circuit may be an NAND logic circuit.

In an embodiment, the logic circuit may be a flip-flop logic circuit.

In an embodiment, the logic circuit may be a D-type flip-flop circuit.

The logic circuit may otherwise be an adder logic circuit.

The complementary energy path adiabatic logic may also be a circuit thatis cascaded with any of the logic circuits mentioned above and with apower clock network in common.

The inventive complementary energy path adiabatic logic is designed tosatisfy the requirements of low power dissipation possessed in the priorarts, high practicability, low design cost, and good reliability. Theprinciple and efficacy of the present invention are described asfollows.

First of all, the circuit operation of the present invention isdiscussed. Referring to FIG. 1, a circuit of single-stage complementaryenergy path adiabatic logic circuit is shown. Although similar to theprior QSERL circuit, presented in [1]-[2] and with complementary powerclocks used therein, in structure, the circuit of the inventivecomplementary energy path adiabatic logic utilizes two sets of P and N-type transistors to lessen the operation limitations resulting from thecircuit itself and complementary power clocks as compared with the QSERLcounterpart. Now the lessening of the operating limitations isexemplified with the complementary power clocks shown in FIG. 2. In theinventive complementary energy path adiabatic logic, since the circuitstructure has been changed, a new “evaluate phase” can be used inreplace of the “hold phase” of the QSERL with the same number of powerclocks inputted. The operation based on such complementary power clocksis generally called “true single-phase clocking”, and lends theinventive complementary energy path adiabatic logic twice the evaluationinterval as compared with the QSERL circuit. Assuming that 1) Vtn and|Vtp| are, respectively, the threshold voltage and absolute value of thethreshold voltage of the N-type MOS transistor and P-type MOStransistor, and 2) Output shown in FIG. 1 is an effective logic LOWinitially, the operation of the inventive complementary energy pathadiabatic logic will be the way described below.

When the inventive complementary energy path adiabatic logic operates inthe evaluate phase, the power clock 50 rises from zero (the lowestvoltage), while the complementary one 60 descends from the highestvoltage. Assuming that PMOS Input turns on the “set of P-type MOStransistors”, it conducts an adiabatic charging operation through thefirst P-type MOS transistor 10 until Output has a voltage reaching themaximum voltage of the power clock 50 minus an absolute value of thethreshold voltage of the P-type transistor |Vtp|. Otherwise, when NMOSInput turns on the “set of N-type MOS transistors”, the complementary(anti-phase) power clock 60 conducts a adiabatic discharging processthrough the first N-type MOS transistor 20 until Output has a voltagereaching the threshold voltage of the N-type transistor Vtn.

According to the above description, the inventive adiabatic logic istotally identical to the prior QSERL presented in [1] and [2] inoperation. Herein, the power clock network of the QSERL is the firstP-type MOS transistor 10 and the first N-type MOS transistor 20 shown inFIG. 1. That is, the inventive adiabatic logic is different from theQSERL counterpart as it requires two more MOS transistors, as can beseen from FIG. 1. In the evaluation network, the combination of the MOStransistors depends upon the purposes of the desired evaluationoperation. On the other hand, when the power clock 50 begins to fall andthe complementary power clock 60 begins to rise, the QSERL enters thehold phase shown in FIG. 2, leading to the output of itself becomingfloating. Correspondingly, the output has a considerably reduced noiseimmunity and thus possibility of erroneous operation of the circuit ofthe QSERL circuit greatly increases. Furthermore, when PMOS Input andNMOS Input of the QSERL circuit keeps constant during the next cycle ofthe power clocks (as shown in FIG. 5( a)), the floating state of theoutput of QSERL becomes longer. By contrast, when the inventiveadiabatic logic enters the hold phase of QSERL shown in FIG. 2, thesecond P-type MOS transistor 40 and the second N-type MOS transistor 30forms in time a set of conductive paths although the first P-type MOStransistor 10 and the first N-type MOS transistor 20 are also turnedoff. In the hold phase of the QSERL circuit, even the input signals ofthe evaluation network changes, the inventive adiabatic logic can stillfinish the evaluation task through the second P-type MOS transistor 40and the second N-type MOS transistor 30 and generate a correct output.By contrast, the QSERL circuit has an erroneous output due to the lackof the second P-type MOS transistor 40 and the second N-type MOStransistor 30.

In this regard, the inventive adiabatic logic almost eliminates theadverse effect brought from the “hold phase” produced by the QSERLcircuit. Even importantly, the inventive adiabatic logic still has theability of evaluation in response to the input signals even though itoperates in the “hold phase” of QSERL. Consequently, the inventiveadiabatic logic can handle up to twice the throughput of the QSERLcircuit.

Almost all available adiabatic logic requires multiple power locks andphases when the multi-stages are used therein, and thus a complicatedtiming control is needed in operation. In addition, some of thecurrently available adiabatic logic requires two complementary circuitsto be coupled as some particular forms such as N-P domino form formulti-stage configuration, so as to operate normally. This results inrelatively more complicated system design and higher realization cost.This is quite different from the case in the inventive adiabatic logicshown in FIG. 3. As shown in FIG. 3, the multi-stage configuration forthe inventive adiabatic logic can be almost totally identical to thetraditional CMOS circuit, that is, with only one set of power clocks incommon as compared with the prior arts where multiple power clocks arerequired and their multiple-stage configurations are even morecomplicated. As a result, the inventive adiabatic logic has been ofsignificant improvement in all of the aspects, as compared with theprior arts. In fact, the inventive adiabatic logic effectively reducesthe complexity and cost of the circuit design and considerably enhancespracticability and application. Although the power clock networkrequires one additional P and N-type MOS transistors for a single-stagecircuit of the inventive adiabatic logic as compared to the QSERL, theinventive adiabatic logic and QSERL have the same number of P anN-transistors when they are in the multi-stage configurations in theirevaluation networks and each of them is with a set of power clocknetwork with four transistors in common, as can be seen from theexamples shown in FIG. 4 and FIG. 7.

As shown in FIG. 4, the inventive adiabatic logic uses MOS transistorsCP1, CN1, CP2 and CN2 of a set of power clock network to realize aninvert chain formed with cascaded four-stage inverters. In the inverterchain, the first inverter is composed of the MOS transistors MP1 andMN1, and the other inverters are also similarly represented. Each stagehas an output, which is forwarded to the next stage thereof. Then, thenext stage performs an evaluation task in response to the output of itsprevious stage and power clocks.

As shown in FIG. 7, the QSERLs are used to form an inverter chainstructure composed of four-stage inverters by using the MOS transistorQP1, QN1, QP2 and QN2 of the power clock network in common. In theinverter chain, the first inverter is composed of the MOS transistorsMP5 and MN5, and the other inverters are also similarly represented. Inthis structure, the required number of the MOS transistors is no morethan that of the QSERL. Assuming that the geometry ratios (W/L) of CP1,CP2, CN1, CN2, MP1, MP2, MP3, MP4, MN1, MN2, MN3, and MN4 are,respectively, the same as those of QP1, QP2, QN1, QN2, MP5, MP6, MP7,MP8, MN5, MN6, MN7, and MN8, wherein W and L are the width and length ofthe MOS transistor, the two cases have the same layout area.

In addition, the structure of the present invention has beendemonstrated through the 0.18-μm CMOS technology of TSMC, inc. In thisdemonstration, the inventive adiabatic logic and QSERL counterpart areused to implement a low-risk D-type flip flop respectively. The resultis the D-type flip flop associated with the present invention has areduction of power-delay (energy) product up to over 50% over the othercase when a power clock having an operation frequency of 25 MHz and itsinverted version thereof are inputted. This shows the present adiabaticlogic can have a significant energy saving.

In addition, the D-type flip flop with the inventive adiabatic logicused therein has been demonstrated that a throughput twice that of theD-type flip flop embedded with the QSERL can be achieved. It is to benoted that the present invention not only can be demonstrated throughTSMC, Inc. and the 0.18-μm technology but can also be demonstrated andutilized by other manufacturing process.

Aside from the good energy efficiency, the present invention alsoeliminates the disadvantages inhered from the prior arts, such as outputfloating. In addition, the noise tolerance of the four-stage inverterchains formed with the present adiabatic logic and QSERL have beenanalyzed regarding their noise tolerance, respectively.

It can be seen the two cases have each erroneous point of time throughFIG. 5 a . In FIG. 5 a , the erroneous point occurs in the time periodlimited to the two dashed lines, respectively, i.e. the time period whenthe adiabatic charging and discharging paths are both turned off in thetwo cases. Within the time period, a pulse noise will make the outputunpredictable in each of the two cases. This is because the noise willresult in an output voltage moving around Switching Point of logic leveltransition and therefore makes the output out of its correct logicstate.

Now refer to FIG. 5 b . When two kinds of pulse noises are imposed onthe outputs of the first stages of the four-stage inverter chains of thetwo cases mentioned above (as depicted in FIG. 5 a ), it can seen boththe two cases have erroneous outputs at there first stages. However, theinventive adiabatic logic can quickly force the output of the firststage to be exempted from the error and get back to its normal statewith the subsequently coming power clock (the subsequently coming powerclock is complementary to the original power clock through which thefirst stage evaluates its output). Since the stage next to the firststage is free from effect on the output of the first stage, a normaloperation can be achieved in the present adiabatic logic. By contrast,there exists a considerable latency in the consecutive stages of thefour-stage inverter chains of QSERL and thus the error occurring at theoutput of the first stage will be accumulated, making the four-stageinverter chain of QSERL totally fail. Therefore, the present adiabaticlogic is demonstrated to have good reliability and efficacy.

Reference

-   [1] V. De and J. D. Meindl, “Complementary adiabatic and fully    adiabatic MOS logic families for gigascale integration,” Proc. ISSCC    Dig. Tech. Papers, pp. 298-299, 1996.-   [2] M.-E. Hwang, A. Raychowdhury, K. Roy, “Energy-Recovery    Techniques to Reduce On-Chip Power Density in Molecular    Nanotechnologies,” IEEE Trans. Circuits Syst. I, vol. 52, pp.    1580-1589, August 2005.

1. A complementary energy path adiabatic logic, comprising: a powerclock network comprising at least one stage including a P-type MOStransistor member, an N-type MOS transistor member, a first P-type MOStransistor, a first N-type MOS transistor, a second N-type MOStransistor, and a second P-type MOS transistor; an evaluation networkcomprising at least one stage including a P-type MOS transistor elementand an N-type MOS transistor element, with the evaluation network beingconnected to an output of the at least one stage of the power clocknetwork; a power clock connected to inputs of the first P-type MOStransistor and the second N-type MOS transistor; and an invertedcomplementary power clock connected to inputs of the second P-type MOStransistor and the first N-type MOS transistor, wherein an output of thefirst P-type MOS transistor is connected to an output of the secondP-type MOS transistor, an output of the first N-type MOS transistor isconnected to an output of the second N-type MOS transistor, the outputof the first P-type MOS transistor is connected to a last stage of theat least one stage of the power clock network, and the output of thefirst N-type MOS transistor is connected to the last stage of the atleast one stage of the power clock network; and wherein the evaluationnetwork evaluates the output of the at least one stage of the powerclock network as the power clock and the inverted complimentary powerclock operate.
 2. The complementary energy path adiabatic logic circuitas claimed in claim 1, wherein each of the at least one stage of theevaluation network is an inverter logic circuit.
 3. The complementaryenergy path adiabatic logic circuit as claimed in claim 2, wherein theinverter logic circuit is a four-stage inverter logic circuit.
 4. Thecomplementary energy path adiabatic logic circuit as claimed in claim 1,wherein each of the at least one stage of the evaluation network is anNOR logic circuit.
 5. The complementary energy path adiabatic logiccircuit as claimed in claim 1, wherein each of the at least one stage ofthe evaluation network is an NAND logic circuit.
 6. The complementaryenergy path adiabatic logic circuit as claimed in claim 1, wherein eachof the at least one stage of the evaluation network is a flip-flop logiccircuit.
 7. The complementary energy path adiabatic logic circuit asclaimed in claim 6, wherein the flip-flop logic circuit is a D-typeflip-flop circuit.
 8. The complementary energy path adiabatic logiccircuit as claimed in claim 1, wherein each of the at least one stage ofthe evaluation network is an adder logic circuit.